The present invention relates to a memory system including a memory device for switching control of a read-only memory (ROM) and a random-access memory (RAM) to allocate addresses to the two memories.
FIG. 1 of the accompanying drawings illustrates a known memory device of the type described. A data signal 1 is read out of a ROM 2 or read out of or written into a RAM 3. The ROM 2 and the RAM 3 are supplied with an address signal 4. Use of either the ROM 2 or the RAM 3 is selected by a control signal 5 applied through a changeover switch 6 to the ROM 2 or the RAM 3. The switching operation of the changeover switch 6 is effected by a ROM/RAM switching signal 8 stored in a switching control unit 7 and generated in response to input signal 10.
With the prior arrangement shown in FIG. 1, either the ROM 2 only is accessed or the RAM 3 only is accessed for one address at a time by the ROM/RAM switching signal 8. The prior memory device has previously been incorporated in computers.
A procedure to be followed by the illustrated memory device before operation of a control program or an operating system (OS) is started is illustrated in FIG. 2 of the accompanying drawings. When the system's power supply is switched on, a central processing unit (CPU) reads the control program or OS from the ROM 2 in a step a, and starts to operate a peripheral device such as a disk drive to execute program transfer from the peripheral device to the RAM 3 in a step b. At this stage, the ROM/RAM switching signal 8 is issued from the switching control unit 7 to actuate the changeover switch 6 for shifting the control signal 5 from the ROM 2 to the RAM 3, thus effecting switching from the ROM 2 to the RAM 3 for the same address area in a step c. The OS is then transferred again into the address area in the RAM 3 so that the OS is fully stored again at executable addresses in a step d.
Since the ROM 2 and the RAM 3 are controlled at the same addresses for the transfer of the OS to the RAM 3, it has been necessary to write the OS once at addresses different from executable addresses, and to transfer the OS again to the executable addresses in the RAM 3 after switching has been effected from the ROM 2 to the RAM 3. Therefore, the OS is required to be transferred twice before it is written into the RAM 3 by the CPU. The above conventional procedure is disadvantageous especially with personal computers in which an entire 64K-byte area is constituted by a RAM since address modification is complex.